The present invention relates to a semiconductor package, and more particularly to a semiconductor package capable of preventing deterioration caused due to heat of a semiconductor chip, as well as preventing reliability degradation therefrom.
With respect to light, slim, short, and small electronics such as a notebook computer, a mobile phone, or a PDA, miniaturization of the semiconductor package mounted on a related component is required, i.e., a printed circuit board (hereinafter, “PCB”).
The semiconductor package is generally structured in such a way that at least one semiconductor chip is loaded. It is necessary to mount such semiconductor packages, and various passive elements needed to transfer signal without characteristic degradation, in order to implement specific electronic circuits set using the semiconductor package. The passive elements are exemplified as a resistor R, an inductor L, and a capacitor C, which can be mounted on PCB with the semiconductor package mounted thereon.
Since the passive elements that are necessary to prevent deterioration of the signal characteristics are mounted on the PCB, there is a problem that the total area of the PCB is unnecessarily enlarged, which hinders the miniaturization of the product. Moreover, since the passive elements are directly mounted on the PCB, there is a problem that lengthening of the signal line can cause a delay in signal transfer. Additionally, there is a problem that noise can be inserted while transferring the signal, whereby prevention of the deterioration of the signal characteristic is limited. Generally, the passive elements occupy the circuit at a weight of about 80 percent, and the passive elements occupy about 50 percent of the total size of the printed circuit board.
Therefore, the passive elements have a significant effect on cost, size and reliability of the electronic machines. There has been researches conducted on a technology for an embedded-type passive element in which the passive elements are embedded in a multi-layered printed circuit board. This approach will allow various components to be integrated as one module to improve mounting density, and does not involve a method for miniaturizing each of components separately.
The technology for implementing the embedded passive element includes a System on Chip (SoC) in which the passive elements are integrally formed in the semiconductor chip and a System in Package in which functional elements are embedded in a package form.
The formation of the passive elements composed of multi-layered metal wiring into wafer level is complicated during the process of forming the multi-layered metal wiring because of warping of the thin thickness of the wafer and the deterioration of the semiconductor chip.
Additionally, during the formation of the passive elements on the multi-layered printed circuit board, a reliability of the semiconductor package is likely to be degraded due to a difference of coefficient thermal expansions (CTE) of the substrate and the multi-layered wiring.